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24LCS52
2K 2.5V I2CTM Serial EEPROM with Software Write Protect
FEATURES
* Single supply with operation down to 2.5V * Low power CMOS technology - 1 mA active current typical - 10 A standby current typical at 5.5V - 5 A standby current typical at 3.0V * Organized as a single block of 256 bytes (256 x 8) * Software write protection for lower 128 bytes * Hardware write protection for entire array * 2-wire serial interface bus, I2CTM compatible * 100kHz (2.5V) and 400kHz (5V) compatibility * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 16 bytes * 3.5 ms typical write cycle time for page-write * 10,000,000 erase/write cycles guaranteed * ESD protection >4,000V * Data retention > 200 years * 8-pin DIP, SOIC or TSSOP packages * Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C
PACKAGE TYPES
PDIP/SOIC
A0 A1 A2 Vss 1 8 Vcc WP SCL SDA
24LCS52
2 3 4
7 6 5
TSSOP
A0 A1 A2 Vss
1 2 3 4
8 7 6 5
Vcc WP SCL SDA
24LCS52
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit Electrically Erasable PROM capable of operation across a broad voltage range (2.5V to 5.5V). This device has a software write protect feature for the lower half of the array, as well as an external pin that can be used to write protect the entire array. The software write protect feature is enabled by sending the device a special command, and once this feature has been enabled, it cannot be reversed. In addition to the software protect feature, there is a WP pin that can be used to write protect the entire array, regardless of whether the software write protect register has been written or not. This allows the system designer to protect none, half or all of the array, depending on the application. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with typical standby and active currents of only 5 A and 1 mA respectively. The device has a page-write capability for up to 16 bytes of data. The device is available in the standard 8-pin DIP, 8-pin SOIC and TSSOP packages.
BLOCK DIAGRAM
A0 A1 A2 WP HV Generator Software write protected area (00h-7Fh) Standard Array SDA SCL Vcc Vss Write Protect Circuitry YDEC SENSE AMP R/W CONTROL
I/O Control Logic
Memory Control Logic
XDEC
I2C is a trademark of Philips Corporation.
(c) 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21166B-page 1
24LCS52
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name VSS SDA SCL VCC A0, A1, A2 WP
PIN FUNCTION TABLE
Function Ground Serial Address/Data I/O Serial Clock +2.5V to 5.5V Power Supply Chip Selects Hardware Write Protect
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65C to +150C Ambient temp. with power applied ................ -65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins............................................. 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.5V to +5.5V Parameter Symbol VIH VIL VHYS VOL ILI ILI ILO CIN, COUT ICC Write ICC Read ICCS Min. .7 VCC .3 VCC -- .40 10 50 10 10 Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Max. Units V V V V A A A pF mA mA A A Conditions
SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current All I/O pins WP pin Output leakage current Pin capacitance (all inputs/outputs) Operating current
.05 VCC
(Note) IOL = 3.0 mA, VCC = 2.5V VIN = 0.1V to 5.5V, WP = Vss WP = VCC VOUT = 0.1V to 5.5V VCC = 5.0V (Note) Tamb = 25C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC
-10 -10 -10 -- -- -- --
3 1 Standby current 30 100 Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL TSU:STA SDA THD:STA TSU:STO
START
STOP
DS21166B-page 2
Preliminary
(c) 1996 Microchip Technology Inc.
24LCS52
TABLE 1-3: AC CHARACTERISTICS
Vcc = 2.5-5.5V STD MODE Min. Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max. 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc = 4.5 - 5.5V FAST MODE Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns
Parameter
Symbol
Units
Remarks
(Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance
TOF TSP TWR
-- -- -- 10M
250 50 10 --
20 +0.1 CB -- -- 10M
250 50 10 --
ns ns ms cycles
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) Byte or Page mode 25C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW TR
SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT THD:STA TAA TBUF THD:DAT TSU:DAT TSU:STO
(c) 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 3
24LCS52
2.0 FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LCS52 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion.
3.5
Acknowledge
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LCS52 does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.6
Device Addressing
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
A control byte is the first byte received following the START condition from the master device. The first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for writing to the write protect register. The control byte is followed by three chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24LCS52 devices on the same bus and are used to determine which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. The device will not acknowledge if you attempt a read command with the control code set to 0110.
FIGURE 3-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
DS21166B-page 4
Preliminary
(c) 1996 Microchip Technology Inc.
24LCS52
The eighth bit of slave address determines if the master device wants to read or write to the 24LCS52 (Figure 32). When set to a one a read operation is selected and when set to a zero a write operation is selected. Operation Read Write Set Write Protect Register Control Code 1010 1010 0110 Chip Select A2 A1 A0 A2 A1 A0 A2 A1 A0 R/W 1 0 0 another acknowledge signal from the 24LCS52 the master device will transmit the data word to be written into the addressed memory location. The 24LCS52 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LCS52 will not generate acknowledge signals (Figure 4-1). If an attempt is made to write to the array when the software or hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled.
FIGURE 3-2:
START
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS R/W A
4.2
Page Write
1
0
1
0 OR
A2
A1
A0
0
1
1
0
A2
A1
A0
4.0
4.1
WRITE OPERATIONS
Byte Write
Following the start signal from the master, the device code(4 bits), the chip select bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LCS52. After receiving
The write control byte, word address and the first data byte are transmitted to the 24LCS52 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24LCS52 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2). If an attempt is made to write to the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled.
FIGURE 4-1:
BUS ACTIVITY MASTER SDA LINE
BYTE WRITE
S T A R T S A C K A C K A C K CONTROL BYTE WORD ADDRESS DATA S T O P P
BUS ACTIVITY
FIGURE 4-2:
BUS ACTIVITY MASTER
PAGE WRITE
S T A R T CONTROL BYTE WORD ADDRESS (n) S T O P
DATA n
DATA n + 15
SDA LINE BUS ACTIVITY
S
A C K A C K A C K A C K A C K
P
(c) 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 5
24LCS52
5.0 ACKNOWLEDGE POLLING 6.0 WRITE PROTECTION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. The 24LCS52 has a software write protect feature that allows the lower half of the array (addresses 00h - 7Fh) to be permanently write protected, as well as a WP pin that can be used to protect the entire array.
6.1
Software Write Protect
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The software write protect feature is invoked by writing to the write protect register. This is done by sending a command similar to a normal write command. As shown in Figure 6-1, the write protect register is written by sending a write command with the slave address set to 0110 instead of 1010 and the address bits and data bits are don't cares. Once the software write protect register has been written, the device will not acknowledge the 0110 control byte. Once the software write protect register has been written, the write protection is enabled and cannot be reversed, even if the device is powered down.
6.2
Send Stop Condition to Initiate Write Cycle
Hardware Write Protect
Send Start
The WP pin can be tied to Vcc, VSS, or left floating. If tied to VCC, the entire array will be write protected, regardless of whether the software write protect register has been written or not. If the WP pin is set to VCC, it will prevent the software write protect register from being written. If the WP is tied to VSS or left floating, then write protection is determined by the status of the software write protect register.
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
FIGURE 6-1:
BUS ACTIVITY MASTER
SETTING WRITE PROTECT REGISTER
S T A R T CONTROL BYTE WORD ADDRESS DATA S T O P
SDA LINE
S
A C K A C K A C K
P
BUS ACTIVITY
DS21166B-page 6
Preliminary
(c) 1996 Microchip Technology Inc.
24LCS52
7.0 READ OPERATION
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 24LCS52 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LCS52 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LCS52 discontinues transmission (Figure 7-2). After this command, the internal address counter will point to the address location following the one that was just read.
7.1
Current Address Read
The 24LCS52 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24LCS52 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LCS52 discontinues transmission (Figure 7-1).
7.3
Sequential Read
7.2
Random Read
Sequential reads are initiated in the same way as a random read except that after the 24LCS52 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LCS52 to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LCS52 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T CONTROL BYTE S T O P
S
A C K DATA N O A C K
P
FIGURE 7-2:
RANDOM READ
S T A R T CONTROL BYTE WORD ADDRESS (n) S T A R T CONTROL BYTE S T O P
BUS ACTIVITY MASTER
S
SDA LINE A C K A C K
S
A C K DATA (n) N O A C K
P
BUS ACTIVITY
FIGURE 7-3:
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
SEQUENTIAL READ
CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X S T O P
P
A C K A C K A C K A C K N O A C K
(c) 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 7
24LCS52
7.4 Contiguous Addressing Across Multiple Devices
8.0
8.1
PIN DESCRIPTIONS
SDA Serial Address/Data Input/Output
The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24LCS52 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to sequentially read across device boundaries.
This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10k for 100 kHz, 1k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
8.3
A0, A1, A2
The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24LCS52 devices may be connected to the same bus by using different chip select bit combinations. These inputs must be connected to either Vcc or Vss.
8.4
WP
This is the hardware write protect pin. It can be tied to VCC, VSS, or left floating. If tied to Vcc, the hardware write protection is enabled. If the WP pin is tied to Vss the hardware write protection is disabled. If the WP pin is left floating, an internal pull down resistor will pull the WP pin to Vss and the hardware write protection will be disabled.
8.5
Noise Protection
The 24LCS52 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
DS21166B-page 8
Preliminary
(c) 1996 Microchip Technology Inc.
24LCS52
NOTES:
(c) 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 9
24LCS52
NOTES:
DS21166B-page 10
Preliminary
(c) 1996 Microchip Technology Inc.
24LCS52
24LCS52 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
24LCS52
--
/P Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body) ST = TSSOP, 8-lead Blank = 0C to +70C I = -40C to +85C 24LCS52 24LCS52T 2K I2C Serial EEPROM 2K I2C Serial EEPROM (Tape and Reel)
Temperature Range: Device:
(c) 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
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9/3/96
All rights reserved. (c) 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21166B-page 12
Preliminary
(c) 1996 Microchip Technology Inc.

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